DFT 2007 - Call for Papers

CALL FOR PAPERS

Overview -- Author Information -- About the Location -- Contact -- Committees

Overview

This symposium provides an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. The topics include (but are not limited to) the following ones:

Yield Analysis, Modeling and Enhancement
Defect/Fault analysis and models; statistical yield modeling; critical area and other metrics.
Repair, Restructuring and Reconfiguration
Repairable logic, reconfiguration, repair; reconfigurable circuit design; DFT for on-line operation.
Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity.
Error Detection, Correction, and Recovery
Self-testing and self-checking design; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy.
Defect and Fault Tolerance
Reliable circuit synthesis; radiation hardened/tolerant processes and design; transient/soft faults and errors.
Dependability Analysis and Validation
Fault injection techniques and environments; dependability characterization of IC and systems.
Emerging Technologies
DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly.
Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, microprocessors
Totally Fail-Safe Design for Critical Applications
Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine and space.

Author Information

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Prospective authors should prepare an extended summary or the full paper (up to 9 pages in the IEEE 6X9 format), to be submitted as PDF file. Uncompressed unencapsulated postscript may also be used when necessary. Submission should be done electronically. Detailed information about the submission process will be made available on the symposium web page:

http://www.dfts.org

We are also interested in panel sessions that involve industrial experiences: please send an email to the Program Chairs with a brief description (1 page maximum) of the panel discussion you would like to propose.

Paper Publication and Presenter Registration:
Papers will be accepted for regular or poster presentation at the symposium. Proceedings will be published by the IEEE Computer Society.

Each accepted paper MUST have at least an author with a paid full registration for the manuscript to be included and published in the proceedings; an author is also expected to attend and present the paper at the Symposium.

Journal Special Issue:
Authors will have the opportunity to submit an extended version of their paper presented at the symposium in a special issue of an archival journal.

Best Paper Award:
A “Best Paper Award” will be awarded by the technical program committee.

Prospective authors should adhere to the following deadlines:

Submission deadline: May 7, 2007
Notification of acceptance: June 7, 2007
Camera ready full papers: July 7, 2007

For general information, contact the General co-Chairs. For paper submission information, contact the Program co-Chairs.

About the Location

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DFT’07 will be held at the Best Western Universo Hotel located in the center of beautiful city of Rome, a UNESCO world heritage site which hosts some of the world's best known works of art and monuments.

Contact

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General Information

Adelio Salsano
University of Rome “Tor Vergata” ITALY
Phone: +39 06 7259-7340
Fax: +39 06 202519
E-mail: salsano@ing.uniroma2.it

Nur Touba
University of Texas at Austin, USA
Phone: +1 512 232 1456
Fax: +1 512 471 5532
E-mail: touba@ece.utexas.edu

Submission Information

Cristiana Bolchini
Politecnico di Milano, ITALY
Phone: +39 02 2399 3619
Fax: +39 02 2399 3411
E-mail: cristiana.bolchini@polimi.it

Yong-Bin Kim
Northeastern University, USA
Phone: +1 617 373 2919
Fax: +1 617 373 8970
E-mail: ybk@ece.neu.edu

Committees

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General co-Chairs

Adelio Salsano
University of Rome “Tor Vergata” ITALY
Phone: +39 06 7259-7340
Fax: +39 06 202519
E-mail: salsano@ing.uniroma2.it

Nur Touba
University of Texas at Austin, USA
Phone: +1 512 232 1456
Fax: +1 512 471 5532
E-mail: touba@ece.utexas.edu

Program co-Chairs

Cristiana Bolchini
Politecnico di Milano, ITALY
Phone: +39 02 2399 3619
Fax: +39 02 2399 3411
E-mail: cristiana.bolchini@polimi.it

Yong-Bin Kim
Northeastern University, USA
Phone: +1 617 373 2919
Fax: +1 617 373 8970
E-mail: ybk@ece.neu.edu

Publicity Chair

Marco Ottavi
Northeastern University, USA
(at Advanced Micro Devices, USA)
E-mail: mottavi@ece.neu.edu

Local Arrangement co-Chairs

Salvatore Pontarelli
University of Rome “Tor Vergata” ITALY
Email: pontarelli@ing.uniroma2.it

Marco Re
University of Rome “Tor Vergata” ITALY
Email: marco.re@uniroma2.it

Program Committee

Jacob Abraham, Univ. of Texas, USA
Bashir Al-Hashimi, Univ. of Southampton, UK
Lorena Anghel, TIMA labs, FRANCE
Cristiana Bolchini, Politec. di Milano, ITALY
Glenn Chapman, Simon Fraser U., CANADA
Minsu Choi, U. of Missouri-Rolla, USA
Luis Entrena, U. Carlos III de Madrid, SPAIN
Michele Favalli, U. of Ferrara, ITALY
Joan Figueras, Univ. Polit. Catalunya SPAIN
Eiji Fujiwara, Tokyo Inst. of Tech., JAPAN
Masaru Fukushi, Tohoku University JAPAN
Dimitris Gizopoulos, U. of Piraeus, GREECE
Susumu Horiguchi, Tohoku University, JAPAN
Chih-Tsun Huang, Nat'l Tsing Hua U., TAIWAN
Hideo Ito, Chiba U., JAPAN
Abhijit Jas, Intel, USA
Wen-Ben Jone Univ. of Cincinnati USA
Yong-Bin Kim, Northeastern U., USA
Israel Koren, UMASS Amherst, USA
Regis Leveugle, TIMA labs, FRANCE
Jien-Chung Lo, U. of Rhode Island, USA
Fabrizio Lombardi, Northeastern U., USA
Martin Margala, U. of Rochester, USA
Cecilia Metra, U. of Bologna, ITALY
Nicola Nicolici, McMaster University CANADA
Marco Ottavi, Northeastern University (AMD) USA
Nohpill Park, Oklahoma State U., USA
Zebo Peng, Linkoping U., SWEDEN
Vincenzo Piuri, U. of Milan, ITALY
Witold Pleskacz, Warsaw U.T., POLAND
Irith Pomeranz, Purdue U., USA
Salvatore Pontarelli, Univ of Rome, ITALY
Maurizio Rebaudengo, Politec. di Torino, ITALY
Sudhakar Reddy, U. of Iowa, USA
Donatella Sciuto, Politec. di Milano, ITALY
Renato Stefanelli, Politec. di Milano, ITALY
Mohammad. Tehranipoor Univ. of Connecticut USA
Joao Paulo Teixeira INESC-ID Lisboa PORTUGAL
Claude Thibeault, Ecole de Tech., CANADA
Nobuo Tsuda, NTT, JAPAN
Raoul Velazco, TIMA labs, FRANCE
Massimo Violante Politec. di Torino ITALY
Moritoshi Yasunaga, Tsukuba U. JAPAN

For more information, visit us on the web at: http://www.dfts.org

The 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'07) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Fault-Tolerant Computing Technical Committee and Test Technology Technical Council (TTTC).